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THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 1 thine electronics, inc. 7 pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz data (lvds) (56-1120mbit/on each lvds channel) clkin THC63LVDM83E cmos/ttl parallel to serial 7 pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz data (lvds) (56-1120mbit/on each lvds channel) clkin THC63LVDM83E cmos/ttl parallel to serial THC63LVDM83E small package / 24bit color lvds transmitter general description the THC63LVDM83E transmitter is designed to support pixel data transmission between host and flat panel display up to 1080p/wuxga resolutions. the THC63LVDM83E converts 28bits of cmos/ttl data into lvds (low voltage differential signaling) data stream. the transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. at a transmit clock frequency of 160mhz, 24bits of rgb data and 4bits of timing and control data (hsync, vsync, de, cont1) are transmitted at an effective rate of 1120mbps per lvds channel. features ? 49pin 0.65mm pitch vfbga package ? wide dot clock range: 8-160mhz suited for tv signal : ntsc(12.27mhz) - 1080p(148.5mhz) pc signal : qvga(8mhz) - wuxga(154mhz) ? 1.2v to 3.3v cmos inputs are supported. ? lvds swing is reducible by rs-pin to reduce emi and power consumption. ? pll requires no external components. ? on chip jitter filtering. ? spread spectrum clock input tolerant. ? power down mode. ? input clock triggering edge is selectable by r/f-pin. ? operates from a single 3.3v supply and 110mw(typ.) at 75mhz. block diagram
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 2 thine electronics, inc. 1234567 a ta6 ta5 ta4 ta3 ta2 ta1 ta0 a b tb4 td3 td2 td1 td0 ta- ta+ b c tb5 tb0 gnd vcc rs tb- tb+ c d tb6 tb1 gnd lvds vcc lvds vcc tc- tc+ d e tc0 tb2 gnd pll vcc r/f tclk- tclk+ e f tc1 tb3 td4 td5 td6 td- td+ f g tc2tc3tc4tc5tc6clkin/pdwn g 1234567 top view ball out
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 3 thine electronics, inc. pin description pin name pin # direction type description ta+, ta- b7, b6 tb+, tb- c7, c6 tc+, tc- d7, d6 td+, td- f7, f6 lvds data out tclk+, tclk- e7, e6 output lvds lvds clock out ta0 ~ ta6 a7,a6,a5,a4,a3,a2,a1 tb0 ~ tb6 c2,d2,e2,f2,b1,c1,d1 tc0 ~ tc6 e1,f1,g1,g2,g3,g4,g5 td0 ~ td6 b5,b4,b3,b2,f3,f4,f5 pixel data input /pdwn g7 h : normal operation l : power down (all outputs are hi-z) rs c5 lvds swing mode, vref select see fig.5, 6 rs lvds swing small swing input support vcc 350mv n/a 0.6 ~ 1.4v 350mv rs=vref gnd 200mv n/a vref is input reference voltage r/f e5 input clock triggering edge select h : rising edge l : falling edge clkin g6 input lv-cmos /ttl input clock vcc c4 power supply pin for cmos input and digital circuit. gnd c3,d3,e3 ground pins for common. lvds vcc d4,d5 power supply pins for lvds outputs. pll vcc e4 power --- power supply pin for pll circuit.
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 4 thine electronics, inc. absolute maximum ratings parameter min max units supply voltage -0.3 +4.0 v lv-cmos/ttl input voltage -0.3 vcc + 0.3 v lvds transmitter output voltage -0.3 vcc + 0.3 v output current -30 30 ma junction temperature +125 c storage temperature -55 +125 c reflow peak temperature +260 c reflow peak temperature time 10 sec maximum power dissipation @+25 c 1.2 w recommended operating conditions symbol parameter min typ max units all supply voltage 3.0 3.3 3.6 v ta operating ambient temperature 0 25 +70 c clock frequency 8 160 mhz
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 5 thine electronics, inc. clkin f ta0, tb1, tc2 f/16 ta1, tb2, tc3 f/8 ta2, tb3, tc4 f/4 ta3, tb4, tc5 f/2 ta4-6, tb0,5,6 tc0 , 1 , 6 , td0-2 steady state low td3-6 steady state high clkin tx0-6 power consumption vcc = 3.0~3.6v, ta= 0~+70oc symbol parameter conditions typ* max units rl=100 , cl=5pf, f=85mhz rs=vcc, (rs=gnd) 42 (34) ma lvds transmitter operating current gray scale pattern 16 (fig.1) rl=100 , cl=5pf, f=160mhz rs=vcc, (rs=gnd) 58 (50) ma rl=100 , cl=5pf, f=85mhz rs=vcc, (rs=gnd) 45 (36) 67 (56) ma i tccw lvds transmitter operating current worst case pattern (fig.2) rl=100 , cl=5pf, f=160mhz rs=vcc, (rs=gnd) 63 (55) 92 (80) ma i tccs lvds transmitter power down current 10 a *typ values are at vcc=3.3v, ta = +25oc 16 grayscale pattern fig.1 16 grayscale pattern worst case pattern x=a,b,c,d fig.2 worst case pattern
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 6 thine electronics, inc. electrical characteristics lv-cmos/ttl dc specifications vcc = 3.0~3.6v, ta= 0~+70oc symbol parameter conditions min typ max units v ih high level input voltage rs=vcc or gnd 2.0 vcc v v il low level input voltage rs=vcc or gnd gnd 0.8 v v ddq 1 small swing voltage 1.2 2.8 v v ref input reference voltage small swing (rs=v ddq /2) v ddq /2 v sh 2 small swing high level input voltage v ref= v ddq /2 v ddq /2 +100mv v v sl 2 small swing low level input voltage v ref= v ddq /2 v ddq /2 -100mv v i inc input current gnd v in vcc 10 a *typ values are at vcc=3.3v, ta = +25oc notes : 1 v ddq voltage defines max voltage of small swing input. it is not an actual input voltage. 2 small swing signal is applied to ta0-6, tb0-6, tc0-6, td0-6 and clkin. lvds transmitter dc specifications vcc = 3.0~3.6v, ta= 0~+70oc symbol parameter conditions min typ max units normal swing rs=vcc 250 350 450 mv vod differential output voltage rl=100 ? reduced swing rs=gnd 120 200 300 mv ? vod change in vod between complementary output states 35 mv voc common mode voltage 1.125 1.25 1.375 v ? voc change in voc between complementary output states rl=100 ? 35 mv i os output short circuit current v out =gnd, rl=100 ? -24 ma i oz output tri-state current /pdwn=gnd, v out =gnd to vcc 10 a *typ values are at vcc=3.3v, ta = +25oc
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 7 thine electronics, inc. clk in 90% 10% 90% 10% t tcit t tcit 5pf 100 ta+ ta- 20% 80% 20% 80% t lvt t lvt v diff lv-cmos/ttl & lvds transmitter ac specifications vcc = 3.0~3.6v, ta= 0~+70oc symbol parameter min typ max units t tcit clk in transition time 5.0 ns t tcp clk in period 6.25 t 125 ns t tch clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/- delay 3t ns t ts lv-cmos/ttl data setup to clk in 2.0 ns t th lv-cmos/ttl data hold from clk in 0.0 ns t lvt lvds transition time 0.6 1.5 ns t top1 output data position0 (t=6.25ns ~ 20ns) -0.15 0.0 +0.15 ns t top0 output data position1 (t=6.25ns ~ 20ns) t/7-0.15 t/7 t/7+0.15 ns t top6 output data position2 (t=6.25ns ~ 20ns) 2t/7-0.15 2t/7 2t/7+0.15 ns t top5 output data position3 (t=6.25ns ~ 20ns) 3t/7-0.15 3t/7 3t/7+0.15 ns t top4 output data position4 (t=6.25ns ~ 20ns) 4t/7-0.15 4t/7 4t/7+0.15 ns t top3 output data position5 (t=6.25ns ~ 20ns) 5t/7-0.15 5t/7 5t/7+0.15 ns t top2 output data position6 (t=6.25ns ~ 20ns) 6t/7-0.15 6t/7 6t/7+0.15 ns t tpll phase lock loop set 10.0 ms *typ values are at vcc=3.3v, ta = +25oc lv-cmos/ttl input fig.3 clkin transmission time lvds output v diff = (ta+) ? (ta-) lvds output load fig.4 lvds output load and transmission time
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 8 thine electronics, inc. rs vod vcc 0.6 ~ 1.4v gnd 200mv 350mv t tc p t ts t th t tch t tcl clk in tx0-tx6 t tcd tclk+ tclk- v ddq gnd gnd v ddq v ref voc v ref v ddq /2 v ddq /2 v ddq /2 v dd q /2 v dd q /2 vod rs vref vcc --- 0.6 ~ 1.4v v ddq /2 gnd --- t tcp t ts t th t tc h t tcl clk in tx0-tx6 t tcd tclk+ tclk- voc vcc gnd gnd vcc vod ac timing diagrams lv-cmos/ttl inputs note : clkin : for r/f=gnd, denote as solid line, for r/f = vcc, denote as dashed line. fig.5 clkin period, high/low time, setup/hold timing small swing inputs note : clkin : for r/f=gnd, denote as solid line, for r/f = vcc, denote as dashed line. fig.6 small swing inputs
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 9 thine electronics, inc. v diff = 0v v diff = 0v tclk+/- t top1 t to p0 t to p6 t to p5 t to p4 t to p3 t to p2 td 6 td 5 td4 td 3 td 2 td1 td 0 td+/- tc 6 tc 5 tc4 tc 3 tc 2 tc1 tc 0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) nex t cy cle previous cycle 2.0v clkin /pdwn tclk+/- 3.0v vcc t tpll v diff = 0v lvds output fig.7 lvds output data position phase lock loop set time fig.8 pll lock set time
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 10 thine electronics, inc. ta- ta+ tb- tb+ tc- tc+ tclk- tclk+ td- td+ ta5 ta6 tb4 tb6 tc0 tc1 tb5 tc2 tc3 tc4 tc5 tc6 vcc lvds vcc lvds vcc pll vcc gnd gnd gnd ta4 ta3 ta2 ta1 tb1 tb0 ta0 tb2 tb3 r/f rs td0 td1 td2 td3 td4 td5 td6 /pwdn clkin r2 r3 r4 r5 r6 r7 g2 g3 g4 g5 g6 g7 b2 b3 b4 b5 b6 b7 r0 r1 g0 g1 b0 b1 1234567 a ta6 ta5 ta4 ta3 ta2 ta1 ta0 a b tb4 td3 td2 td1 td0 ta- ta+ b c tb5 tb0 gnd vcc rs tb- tb+ c d tb6 tb1 gnd lvds vcc lvds vcc tc- tc+ d e tc0 tb2 gnd pll vcc r/f tclk- tclk+ e f tc1 tb3 td4 td5 td6 td- td+ f g tc2 tc3 tc4 tc5 tc6 clkin /pdwn g 1234567 top view board layout example
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 11 thine electronics, inc. lvds-rx THC63LVDM83E lvds-rx tclk+ tclk- ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVDM83E THC63LVDM83E ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic THC63LVDM83E THC63LVDM83E note 1) cable connection and disconnection don?t connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection connect the each gnd of the pcb which thc63l vdm83e and lvds-rx on it. it is better for emi reduction to place gnd cabl e as close to lvds cable as possible. 3) multi drop connection multi drop connection is not recommended. 4) asynchronous use asynchronous using such as following systems are not recommended.
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 12 thine electronics, inc. package 1234567 a b c d e f g pin a1 corner 5.0 1 2 3 4 5 6 7 a b c d e f g pin a1 corner 3.90 0.3 0.3 top view bottom view side view unit : mm
THC63LVDM83E_rev.1.30_e copyright?2012 thine electronics, inc. 13 thine electronics, inc. notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be foun d in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industria l ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriat e measures to the product. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conduct or product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. thine electronics, inc. sales@thine.co.jp

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